Microchip enters memory infrastructure market

As the computational demands of artificial intelligence (AI) and machine learning workloads accelerate, traditional parallel attached DRAM memory has presented a major roadblock for next-generation CPUs, which require an increased number of memory channels to deliver more memory bandwidth. The SMC 1000 8x25G enables CPUs and other compute-centric SoCs to utilize four times the memory channels of parallel attached DDR4 DRAM within the same package footprint. Microchip’s serial memory controllers deliver higher memory bandwidth and media independence to these compute-intensive platforms with ultra-low latency.

The SMC 1000 8x25G interfaces to the CPU via 8-bit Open Memory Interface (OMI)-compliant 25 Gbps lanes and bridges to memory via a 72-bit DDR4 3200 interface. A CPU or SoC with OMI support can utilize a broad set of media types with different cost, power and performance metrics without having to integrate a unique memory controller for each type. In contrast, CPU and SoC memory interfaces today are typically locked to specific DDR interface protocols, such as DDR4, at specific interface rates. The SMC 1000 8x25G is the first memory infrastructure product in Microchip’s portfolio that enables the media-independent OMI interface.

“IBM customer workload requirements are increasingly memory-intensive, which is why we have made the strategic decision for POWER processor memory interfaces to utilize OMI standard interfaces to increase memory bandwidth. IBM appreciates the partnership with Microchip to deliver this solution”, said Steve Fields, chief architect of IBM Power Systems.